my hunch is that this circuit is causing the trigger. I also think that C1 is probably responsible.
Ah, thanks for that.
I thought there might be some cascading triggers going on between the channels, but I hadn't had a chance to pull out the board and measure to verify. I take it the ISP reset pin is connected in parallel to 4Y?
I couldn't work out how to hold the pin in reset for programming unless 1B was held high, but it occurred to me this morning that parallel would work just fine but it didn't seem right that they would be floating. The series junction back to 4Y makes so much more sense. Now to trace that down...
Being a nested NAND gate, the reset line to the AVR will go low when 4Y goes high. And 4Y will go high if either 4A OR 4B are pulled low, right? Since 4B seems rather innocuous with a boring 10k resistor to Vcc, I agree that 4A seems to be the interesting circuit.
So, 4A passes through a 2k2 resistor to the anode of the tantalum capacitor, with the cathode grounded through the via. A short in this cap would pull the reset pin low, but i would guess such a short would likely be constant.
From the cap, we find ourselves at a 1M resistor in parallel with a reverse biased diode. The resistor pulls 4A up to the potential of the shared trace, while the diode would quickly sink any current on 4A should the trace be grounded...
On the other side of the diode/resistor pair, we have the 3k3 triplet you mentioned, which are tied to ground alongside the zener diode, which appears to tie back into the unregulated DC bus, which is what is measured across C1. Assaf, can you verify that? The via on the zener pokes through adjacent to the tea water solenoid relay and runs back toward the hot rail that powers the relay coils. It could go someplace else, but I don't see any likely candidates.
No matter the voltage source, the triplet resistors keep the reverse current flowing through the zener diode which holds 4A at the zener voltage. If the supply voltage to the zener is disrupted, the resistors quickly pull 4A low through the diode and the Schmitt trigger will cascade from 4Y to 1Y and pull the reset line low. The 1M resistor should create a relatively long charge time on the tantalum cap, which should make a reset even last some minimum time after the zener voltage is restored before bringing 1Y back high.
An open circuit in the zener would likely cause the same result.
If the ground reference for the resistor triplet were dropped out, there would be no zener voltage, but I don't think this would trigger the Schmitt as it needs at least one line to be pulled low.
Am I digesting this bit of the circuit properly?
If so, it seems that the watchdog circuit is likely the mechanism by which an intermittent short in C1 or the rectifier would be pulling the reset line low, but it would be doing its job in doing so. The zener should be quite tolerant of a wide range of input voltage so long as it exceeds the zener breakdown voltage, right?
Does 4Y also go to 2A and 2B? It appears that 2Y charges the capacitor on 3A and 3B, which in turn holds 3Y low until 2A or 2B drops out. I still need to track down 3Y, but I suspect it heads over and resets the mux/demux chips. It makes sense if it's all tied back to the zener voltage.