La Marzocco GS/3 Sometimes Reboots with Tea Button - Page 6

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Jake_G
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#51: Post by Jake_G » Jan 14, 2020, 10:16 am

AssafL wrote:...
my hunch is that this circuit is causing the trigger. I also think that C1 is probably responsible.

Ah, thanks for that.

I thought there might be some cascading triggers going on between the channels, but I hadn't had a chance to pull out the board and measure to verify. I take it the ISP reset pin is connected in parallel to 4Y?

I couldn't work out how to hold the pin in reset for programming unless 1B was held high, but it occurred to me this morning that parallel would work just fine but it didn't seem right that they would be floating. The series junction back to 4Y makes so much more sense. Now to trace that down...

Being a nested NAND gate, the reset line to the AVR will go low when 4Y goes high. And 4Y will go high if either 4A OR 4B are pulled low, right? Since 4B seems rather innocuous with a boring 10k resistor to Vcc, I agree that 4A seems to be the interesting circuit.

So, 4A passes through a 2k2 resistor to the anode of the tantalum capacitor, with the cathode grounded through the via. A short in this cap would pull the reset pin low, but i would guess such a short would likely be constant.

From the cap, we find ourselves at a 1M resistor in parallel with a reverse biased diode. The resistor pulls 4A up to the potential of the shared trace, while the diode would quickly sink any current on 4A should the trace be grounded...

On the other side of the diode/resistor pair, we have the 3k3 triplet you mentioned, which are tied to ground alongside the zener diode, which appears to tie back into the unregulated DC bus, which is what is measured across C1. Assaf, can you verify that? The via on the zener pokes through adjacent to the tea water solenoid relay and runs back toward the hot rail that powers the relay coils. It could go someplace else, but I don't see any likely candidates.

No matter the voltage source, the triplet resistors keep the reverse current flowing through the zener diode which holds 4A at the zener voltage. If the supply voltage to the zener is disrupted, the resistors quickly pull 4A low through the diode and the Schmitt trigger will cascade from 4Y to 1Y and pull the reset line low. The 1M resistor should create a relatively long charge time on the tantalum cap, which should make a reset even last some minimum time after the zener voltage is restored before bringing 1Y back high.

An open circuit in the zener would likely cause the same result.

If the ground reference for the resistor triplet were dropped out, there would be no zener voltage, but I don't think this would trigger the Schmitt as it needs at least one line to be pulled low.

Am I digesting this bit of the circuit properly?

If so, it seems that the watchdog circuit is likely the mechanism by which an intermittent short in C1 or the rectifier would be pulling the reset line low, but it would be doing its job in doing so. The zener should be quite tolerant of a wide range of input voltage so long as it exceeds the zener breakdown voltage, right?

Thanks again.

Cheers!

- Jake

*Edit*
Does 4Y also go to 2A and 2B? It appears that 2Y charges the capacitor on 3A and 3B, which in turn holds 3Y low until 2A or 2B drops out. I still need to track down 3Y, but I suspect it heads over and resets the mux/demux chips. It makes sense if it's all tied back to the zener voltage.

ira
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#52: Post by ira » Jan 14, 2020, 1:36 pm

Isn't the red line 5V? Looking at the circuit, I'd guess the wider lines are power and ground and the skinny one's are signals. or does the reset go under the chip and disappear.? From the way you drew the red lines it looks like pins 1, 2 and 14 are connected.

Ira

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Jake_G
Team HB

#53: Post by Jake_G » Jan 14, 2020, 6:43 pm

ira wrote:Isn't the red line 5V? Looking at the circuit, I'd guess the wider lines are power and ground and the skinny one's are signals. or does the reset go under the chip and disappear.? From the way you drew the red lines it looks like pins 1, 2 and 14 are connected.

Ira
Negative. Pins 1 and 2 are tied to 11 (thanks again, Assaf), and so is the red line, but none of these are tied to 14, which is Vcc. The red line appears to hit 14, but it does slide under the chip and tie into the output of 11.

Cheers!

- Jake

ira
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#54: Post by ira » Jan 14, 2020, 7:08 pm

In that case it looks like pin 13 is the RC controlling the power on reset and pin 12 is always pulled high. Though I don't understand why they seem to be on different power connections? FWIW, you will probably need the reset to go below 2V before it triggers a reset so it takes a lot of noise. The could set the brownout to trigger as high as 3.8 V which is what I think would probably trigger if the cause was drooping voltage.

Ira

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AssafL

#55: Post by AssafL » Jan 15, 2020, 2:21 am

ira wrote:Isn't the red line 5V? Looking at the circuit, I'd guess the wider lines are power and ground and the skinny one's are signals. or does the reset go under the chip and disappear.? From the way you drew the red lines it looks like pins 1, 2 and 14 are connected.

Ira
Somewhat misleading as the opposite side of the PCB has some large ground planes (with tracks inbetween the planes).

So some of the Vias are actually ground. But to your point most of the Vcc tracks are actually thicker.
Scraping away (slowly) at the tyranny of biases and dogma.

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AssafL

#56: Post by AssafL » Jan 15, 2020, 2:28 am

ira wrote:In that case it looks like pin 13 is the RC controlling the power on reset and pin 12 is always pulled high. Though I don't understand why they seem to be on different power connections? FWIW, you will probably need the reset to go below 2V before it triggers a reset so it takes a lot of noise. The could set the brownout to trigger as high as 3.8 V which is what I think would probably trigger if the cause was drooping voltage.

Ira
My guess is - and what I was looking for - is that you pull the reset as close as you can to the transformer so as not to drag a shutdown event. You would decouple the 7805 regulator with additional electrolytic caps that can keep the CPU and thus the SSRs activated for quite some time.

So a safe(r) approach is to tap the 16V and when it drops trigger a reset.

To be even safer (and some machinery does this) is to get a voltage from the transformer tap - and trigger if you miss a cycle or two. For an espresso machine which has almost no moving parts and can function almost stateless this is overkill.

But a relay that keeps the 3-way open for 30 seconds after power down may be annoying.
Scraping away (slowly) at the tyranny of biases and dogma.

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AssafL

#57: Post by AssafL » Jan 15, 2020, 3:26 am

Jake_G wrote: Ah, thanks for that.

I thought there might be some cascading triggers going on between the channels, but I hadn't had a chance to pull out the board and measure to verify. I take it the ISP reset pin is connected in parallel to 4Y?

I couldn't work out how to hold the pin in reset for programming unless 1B was held high, but it occurred to me this morning that parallel would work just fine but it didn't seem right that they would be floating. The series junction back to 4Y makes so much more sense. Now to trace that down...

Being a nested NAND gate, the reset line to the AVR will go low when 4Y goes high. And 4Y will go high if either 4A OR 4B are pulled low, right? Since 4B seems rather innocuous with a boring 10k resistor to Vcc, I agree that 4A seems to be the interesting circuit.

So, 4A passes through a 2k2 resistor to the anode of the tantalum capacitor, with the cathode grounded through the via. A short in this cap would pull the reset pin low, but i would guess such a short would likely be constant.

From the cap, we find ourselves at a 1M resistor in parallel with a reverse biased diode. The resistor pulls 4A up to the potential of the shared trace, while the diode would quickly sink any current on 4A should the trace be grounded...

On the other side of the diode/resistor pair, we have the 3k3 triplet you mentioned, which are tied to ground alongside the zener diode, which appears to tie back into the unregulated DC bus, which is what is measured across C1. Assaf, can you verify that? The via on the zener pokes through adjacent to the tea water solenoid relay and runs back toward the hot rail that powers the relay coils. It could go someplace else, but I don't see any likely candidates.

No matter the voltage source, the triplet resistors keep the reverse current flowing through the zener diode which holds 4A at the zener voltage. If the supply voltage to the zener is disrupted, the resistors quickly pull 4A low through the diode and the Schmitt trigger will cascade from 4Y to 1Y and pull the reset line low. The 1M resistor should create a relatively long charge time on the tantalum cap, which should make a reset even last some minimum time after the zener voltage is restored before bringing 1Y back high.

An open circuit in the zener would likely cause the same result.

If the ground reference for the resistor triplet were dropped out, there would be no zener voltage, but I don't think this would trigger the Schmitt as it needs at least one line to be pulled low.

Am I digesting this bit of the circuit properly?

If so, it seems that the watchdog circuit is likely the mechanism by which an intermittent short in C1 or the rectifier would be pulling the reset line low, but it would be doing its job in doing so. The zener should be quite tolerant of a wide range of input voltage so long as it exceeds the zener breakdown voltage, right?

Thanks again.

Cheers!

- Jake

*Edit*
Does 4Y also go to 2A and 2B? It appears that 2Y charges the capacitor on 3A and 3B, which in turn holds 3Y low until 2A or 2B drops out. I still need to track down 3Y, but I suspect it heads over and resets the mux/demux chips. It makes sense if it's all tied back to the zener voltage.
Jake - spectacular job reverse engineering the circuit.

Yes - 4Y goes to 2A and 2B - I wonder what 3Y is used for.

(Note: Notice the number of test pads around the components - Gicar take these watchdog circuits very seriously and test them on their bed of nails setup...).

In any case, the Zener is about a 5.2V Zener which places the voltage on the "tantalum" (is it Tantalum?) at about 8.4V which becomes 5.6V at the pin after the resistors.

Note that the Zener isn't regulating the voltage on the "tantalum". All it does is shifts the C1 voltage down 5.2V (it acts as a constant series voltage drop). the voltage at the "tantalum" is thus V(C1) - (5.2) in volts. Add to that the resistance ratios (I am using the measured values rather than the actual resistors) of 5.6V out to 8.4V in so the voltage divider ratio is 0.66666...

V(4B) = 0.67 x (V(C1) - 5.2)

So to Ira's point The transition to low (for the 74HCT version) happens at about 1V. So approximately:

V(4B) = 1V = 0.67 x (V(C1) - 5.2) or

V(C1) = 1/0.67 + 5.2 = 6.7V

Which is rather low... But sufficient for the 7805 to hold on for dear life and the circuit to operate marginally. Maybe some other part of the circuit clamps it down quicker. For example, 1A has a rather large ceramic in parallel to the resistor. While the resistor sets the bias, the capacitor, given a fast spike - may trigger 1A.

So 3Y... It's output isn't a reset. It goes to the ATE port, and most interestingly, it operates RL7 - that free relay we got from Gicar that isn't connected to anything. It is the "power on" relay. Reset on 2Y pulls it down through the diode.
Scraping away (slowly) at the tyranny of biases and dogma.

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Jake_G
Team HB

#58: Post by Jake_G » Jan 15, 2020, 10:25 am

AssafL wrote:Jake - spectacular job reverse engineering the circuit.
I try :wink:
AssafL wrote:Yes - 4Y goes to 2A and 2B - I wonder what 3Y is used for.
I think I figured that out.
AssafL wrote:(is it Tantalum?)
The form factor and polarity suggests so. Any other capacitor would appear to be installed backwards, since the stripe is not on the ground plane as expected.
AssafL wrote:Note that the Zener isn't regulating the voltage on the "tantalum". All it does is shifts the C1 voltage down 5.2V (it acts as a constant series voltage drop). the voltage at the "tantalum" is thus V(C1) - (5.2) in volts. Add to that the resistance ratios (I am using the measured values rather than the actual resistors) of 5.6V out to 8.4V in so the voltage divider ratio is 0.66666...
I realized that the Zener was simply acting as a voltage shifter last night. Makes sense. So, the 1M resistor isn't just to time the charge of the tantalum cap, but also to pull the voltage down from 8.4 to less than 6V for compliance of the 74HC. The Ii on the inputs is really low (like 0.1nA), so there must be another current draw downstream of the 1M resistor to get the voltage down to 5.6V, or am I misunderstanding the voltage divider reference you gave? I agree that Vout at the Zener should be VC1 - VZener. I'm trying to figure out how V4A drops appreciably from Vout, as I don't see any current draws on the circuit to keep the voltages from equalizing after the Zener? Obviously, I believe your measurements, just scratching my head on the "how?" piece.
AssafL wrote:Which is rather low... But sufficient for the 7805 to hold on for dear life and the circuit to operate marginally. Maybe some other part of the circuit clamps it down quicker. For example, 1A has a rather large ceramic in parallel to the resistor. While the resistor sets the bias, the capacitor, given a fast spike - may trigger 1A.
I'm with you for the most part, but what is the 7805? Also, do you mean 4B? 1A is tied in parallel to 1B on the output of 4Y, right? Also, speaking of the resistor/capacitor pair feeding 4B, what does the capacitor do? The resistor is functioning as a pull up resistor to Vcc, and with 0.1nA flowing through the input, there is no voltage drop across the resistor except for transient events. So, given that the capacitor in parallel is never charged, what is it there for?
AssafL wrote:So 3Y... It's output isn't a reset. It goes to the ATE port, and most interestingly, it operates RL7 - that free relay we got from Gicar that isn't connected to anything. It is the "power on" relay. Reset on 2Y pulls it down through the diode.
I see a different path when I trace 3Y. It looks to me that RL7 is fired from the TPIC6C595 just like all the other outputs and 3Y is landed on the G terminal (pin 8, through the via) which is held low to enable the outputs. From there, the trace on the back side goes to the 2nd pin on the 4 pin "diagnostic" port through the final via. Strangely, that trace supplies the ground reference for C2 (what would opening C2 do to the 5V supply?) and then snakes back to pin 13 on the MM74HC595 shift register, which is again G.

So, it appears that the watchdog does 4 things when triggered by C1 dropping below ~6.7V:
  • Pull the reset pin on the AVR low.
  • Clear the serial data from the shift register (oddly, the TPIC6C595 has the CLR pin grounded?)
  • Remove C2 from the 5V circuit (why?)
  • Disable the outputs of both shift registers
It all makes sense to me with the exception of the voltage divider and the cap on 4B, but my brain must be foggy. I am probably just hung up on something silly. Otherwise, it looks to me like I'm still hunting for a component that, when the tea solenoid relay opens, might be causing enough of a voltage disruption at C1 that there is a transient dip below 6.7V, and then it's lights out for the AVR...

Thanks again for your persistent help with this.

Cheers!

- Jake

ira
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#59: Post by ira » Jan 15, 2020, 2:08 pm

Unless you get a scope with a good trigger mechanism and memory, you're still guessing that reset is causing the problem. Sadly, that's going to be a hard problem to catch. If you were local, I'd bring my tools and we'd figure out if that's the problem, but if you really think it's that 100uf electrolytic, just change it and the question will be answered, or pull it out and measure the capacitance. Seems silly to go through the trouble of making an external reset that triggers on low voltage when the processor has that built in. Normally you'd build a circuit to hold it in reset so that everything it depends on is alive before it starts. If it's really an Atmel Mega, there's really no reason to go through all that trouble which makes me wonder what were missing. Unless they used up 100% of the code space and didn't have anything left to check status on startup. They charge enough for that board that they should never have hit a problem like that.

Not that I don't love the speculation!

Ira

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AssafL

#60: Post by AssafL » replying to ira » Jan 15, 2020, 3:10 pm

I can't find any other connection to the 1M resistor...

The 74HCT input leakage is 1uA. And the electrolytic/tantalum can be much larger. 1uA on a 1M resistor is a volt drop.

Seems like a oddly inconsistent way to set a voltage for a watchdog....

I didn't retrace the second reset through 3.
Yes I agree. I think this may be a symptom of an industrial electronics design where you run reset lines to subsystems. Not important here - but the practices would be ingrained...

For the Cap - I'd use an ESR meter... Some caps deteriorate but still keep decent capacitance (at an oddly high ESR).
Scraping away (slowly) at the tyranny of biases and dogma.